System, method, and computer program product for interfacing one or more storage devices with a plurality of bridge chips

ABSTRACT

Methods, apparatus, and systems, for interfacing one or more storage devices with a plurality of bridge chips. An apparatus may include a memory, a communication bus coupled to a device, and a processor communicatively coupled to the communication bus and the memory. The processor may be configured to implement storage traffic between a storage device and a central processor via a first storage port of a first bridge chip of a plurality of bridge chips. The processor may be further configured to multiplex, by the first bridge chip, the storage traffic to at least one bridge chip of the plurality of bridge chips, and distribute data across the plurality of bridge chips to produce a data distribution enabling each of the bridge chips to communicate with each other.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. non-provisionalapplication Ser. No. 12/498,162, filed Jul. 6, 2009, wherein theforegoing application is incorporated by reference in its entirety forall purposes.

FIELD OF THE INVENTION

The present invention relates to storage systems, and more particularlyto storage systems including bridge device topologies.

BACKGROUND

Often, memory systems use a bridge chip topology for translatingcommands associated with one protocol to another protocol associatedwith a drive being utilized. Typical bridge device topologies include abridge coupled to a drive. In these cases, the single bridge typicallysupports multiple output devices on multiple ports.

If the drive is much faster than the bridge, then the performance of thedrive is limited by the bridge and a single drive unit will not see theperformance of the drive. Rather, the unit will see the performance ofthe bridge. There is thus a need for addressing these and/or otherissues associated with the prior art.

SUMMARY

A system, method, and computer program product are provided forinterfacing one or more storage devices with a plurality of bridgechips. One or more storage devices are provided. Additionally, aplurality of bridge chips are provided. Furthermore, at least onemultiplexing device is provided for interfacing the one or more storagedevices with the plurality of bridge chips.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a system for interfacing one or more storage devices with aplurality of bridge chips, in accordance with one embodiment.

FIG. 2 shows a system for interfacing one or more storage devices with aplurality of bridge chips, in accordance with another embodiment.

FIG. 3 shows a system for interfacing one or more storage devices with aplurality of bridge chips, in accordance with another embodiment.

FIGS. 4A-4B show systems for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with another embodiment.

FIGS. 5A-5C show systems for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with variousembodiments.

FIG. 6 shows a method for interfacing one or more storage devices with aplurality of bridge chips, in accordance with one embodiment.

FIG. 7 illustrates an exemplary system in which the various architectureand/or functionality of the various previous embodiments may beimplemented.

DETAILED DESCRIPTION

FIG. 1 shows a system 100 for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with one embodiment. Asshown, the system 100 includes one or more storage devices 102.

In the context of the present description, a storage device refers toany device capable of storing data. For example, in various embodiments,the storage device 102 may include, but is not limited to, a Serial ATA(SATA) drive, a Serial Attached SCSI (SAS) drive, a Fibre Channel (FC)drive, or a Universal Serial Bus (USB) drive, and/or any other storagedevice.

Additionally, the system 100 includes a plurality of bridge chips 104.In the context of the present description, a bridge chip refers to anydevice capable of performing a protocol translation. For example, invarious embodiments, the bridge chips 104 may include an SAS/SATA bridge(e.g. an SAS to SATA bridge, etc.), a USB/SATA bridge (e.g. a USB toSATA bridge, etc.), an FC/SATA bridge (e.g. an FC to SATA bridge, etc.),PCI/PCIe to SAS/SATA bridge, or any device capable of performing aprotocol translation.

Furthermore, at least one multiplexing device 106 is provided forinterfacing the one or more storage devices 102 with the plurality ofbridge chips 104. In the context of the present description, amultiplexing device refers to any device capable of performingmultiplexing, For example, in various embodiments, the multiplexingdevice may include a multiplexer, a bridge chip, a bridge, or any otherdevice (e.g. hardware and/or software, etc.) capable of performingmultiplexing.

In various embodiments, the interfacing may include a direct connectionor an indirect connection. In either case, the multiplexing device 106may provide an interface such that the storage devices 102 maycommunicate with the plurality of bridge chips 104. In this way,multiple bridge chips may be utilized in a storage system. Thus, theresources associated with a bridge chip may be solely dedicated to aparticular device (e.g. a port, translation function, etc.). Of course,the resources of the bridge chip may be allocated in any manner desired.

More illustrative information will now be set forth regarding variousoptional architectures and features with which the foregoing frameworkmay or may not be implemented, per the desires of the user. It should bestrongly noted that the following information is set forth forillustrative purposes and should not be construed as limiting in anymanner, Any of the following features may be optionally incorporatedwith or without the exclusion of other features described.

FIG. 2 shows a system 200 for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with another embodiment.As an option, the present system 200 may be implemented in the contextof the details of FIG. 1. Of course, however, the system 200 may beimplemented in any desired environment. it should also be noted that theaforementioned definitions may apply during the present description.

As shown, the system 200 includes a storage device 202. In this case,the storage device 202 includes a SATA drive. Additionally, the system200 includes a plurality of bridge chips 204.

In various embodiments, the bridge chips may include an SAS/SATA bridge(e.g. an SAS to SATA bridge, etc.), a USB/SATA bridge (e.g. a USB toSATA bridge, etc.), an FC/SATA bridge (e.g. an FC to SATA bridge, etc.),or any device capable of performing a protocol translation. In thiscase, the bridge chips 204 include an SAS/SATA bridge.

Furthermore, at least one multiplexer 206 is provided for interfacingthe storage device 202 with the bridge chips 204. In this case, themultiplexer 206 includes a SATA multiplexer. Additionally, themultiplexer 206 may include a plurality of ports.

For example, the multiplexer 206 may include a plurality of input ports.The input ports may be connected to the storage device 202.Additionally, the multiplexer 206 may include a plurality of outputports. The output ports may be connected to the plurality of bridgechips 204. In this case, a number of the output ports may be dividedequally and allocated to each of the bridge chips 204.

In one embodiment, the multiplexer 206 may be configured such that eachof the plurality of ports are active at the same time. Furthermore, oneof the plurality of bridge chips 204 may be connected to a group of theplurality of ports.

As shown in FIG. 2, as an option, a communication link 208 may beprovided between one or more of the bridge chips 204. In one embodiment,the communication link 208 may be configured such that each of thebridge chips 204 are capable of communicating with the other bridgechips 204.

As an option, the communication link 208 may be configured to beutilized for error recovery. As another option, the communication link208 may be configured to be utilized for vender unique communication. Asshown further in FIG. 2, each of the plurality of bridge chips 204 maybe dedicated to a single Serial Attached SCSI (SAS) port.

In this way, storage systems using storage devices (e.g. SATA drives,etc.) that are much faster than an attached bridge will not be limitedby the bridge. This may be accomplished by using multiple bridgesconnected to a multiplexing device.

As shown in FIG. 2, a SATA multiplexer is utilized. All ports of theSATA multiplexer may be active at the same time. The bridge chips maythen use all of their resources for a single SAS port.

As noted, there may also be a communication path between the bridge chipfor error recovery and other vendor unique communication. This maygreatly improve the bridge performance for a single port since all thebridge resources may be used to drive one port and not two ports. Itshould be noted that the performance may then be based on multiplebridge chips and not one bridge chip. This allows each bridge chip tofocus resources on a particular bridge function.

In one embodiment, the SATA multiplexer may be implemented using anumber of tags from a first port and a number of tags on a second port.The tags on a third port may then be dedicated to the storage device.For example, the multiplexer may be implemented using tags 0-15 fromport A and 0-15 on the port B, and then queuing tags 0-31 on port C tothe SATA drive.

FIG. 3 shows a system 300 for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with another embodiment.As an option, the present system 300 may be implemented in the contextof the functionality and architecture of FIGS. 1-2. Of course, however,the system 300 may be implemented in any desired environment. Again, theaforementioned definitions may apply during the present description.

As shown, a SATA drive 302 is in communication with multiple bridgechips 304. In this case, a SATA multiplexer 306 interfaces the SATAdrive 302 and the bridge chips 304. Further, multiple communicationlinks 308 are provided.

The communication links 308 may include any type of communication pathcapable of being used to communicate between bridge chips. In variousembodiments, the communication links 308 may be utilized for errorrecovery, vendor unique communication, and/or any other type ofcommunication between bridge chips.

The bridge chips 304 are capable of using all of the resources for asingle SAS port. As shown, each of the bridge chips 304 are dedicated toone SAS port 310. This may greatly improve the bridge performance for asingle port since all the bridge resources may drive only one port.

It should be noted that any number of bridge chips may be utilized withone or more multiplexing devices. In one embodiment, the number ofbridge chips used in the system may be equal to the number of SAS portspresent. Of course, any number of bridge chips may be utilized.

FIGS. 4A-4B show systems 400 for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with another embodiment.As an option, the present systems 400 may be implemented in the contextof the functionality and architecture of FIGS. 1-3. Of course, however,the systems 400 may be implemented in any desired environment. Theaforementioned definitions may apply during the present description.

As shown, a plurality of storage devices 402 are provided. Further, oneor more bridge chips 404 dedicated to interfacing with devices coupledto the storage devices 402 (e.g. device ports, etc.) are provided.Additionally, one or more bridge chips 406 may be utilized as amultiplexing device.

Thus, if the resources are maxed out on one of the bridge chips 404,data may be distributed across the bridge chips 406, where at least oneof the bridge chips 406 include multiplexer type functionality. Inanother embodiment, a multiplexer may be utilized, and additionally,functions may be spread across multiple bridges. Accordingly, a bridgechip may be used instead of a multiplexer, or in addition to multiplexerto perform multiplexing functionality.

FIGS. 5A-5C show systems 500 for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with variousembodiments. As an option, the present systems 500 may be implemented inthe context of the functionality and architecture of FIGS. 1-4. Ofcourse, however, the systems 500 may be implemented in any desiredenvironment. Further, the aforementioned definitions may apply duringthe present description.

As shown in FIGS. 5A-5C, a plurality of storage devices 502 areprovided. Further, a plurality of bridge chips 504 dedicated tointerfacing with devices coupled to the storage devices 502 (e.g. deviceports, etc.) are provided. Additionally, one or more bridge chips 506may be utilized as a multiplexing device.

If the resources are maxed out on one of the bridge chips 504, data maybe distributed across the multiple bridge chips 506, where at least oneof the bridge chips 506 include multiplexer type functionality. As shownin FIG. 5C, a multiplexer 508 may be utilized, and additionallyfunctions may be spread across the multiple bridges 506. It should benoted that any of the bridge chips 504 and 506 may be linked to anyother bridge chip using one or more communication links 510.

FIG. 6 shows a method 600 for interfacing one or more storage deviceswith a plurality of bridge chips, in accordance with one embodiment. Asan option, the present method 600 may be implemented in the context ofthe functionality and architecture of FIGS. 1-5. Of course, however, themethod 600 may be carried out in any desired environment. Once again,the aforementioned definitions may apply during the present description.

As shown, a command is sent from one of a plurality of bridge chips. Seeoperation 602. The command may include any command capable of being sentfrom a bridge chip. For example, in various embodiments, the command mayinclude a read command, a write command, a FORMAT command, and/or anyother command.

In one embodiment, the command may be a command that was translated froma first protocol to a second protocol. In this case, the bridge chip mayhave translated the command. Further, sending the command from thebridge chip may include relaying a command using the bridge chip. Thisrelaying may include translating the command.

The command is then received at one or more storage devices. Seeoperation 604. In this case, the command is communicated utilizing oneor more multiplexing devices interfacing the one or more storage deviceswith the plurality of bridge chips.

Thus, in one embodiment, the command may be received by one of thebridges in a first format associated with a first protocol. The bridgemay then translate the command to a second format associated with asecond protocol.

The bridge may then send the command to the storage device. Amultiplexing device may then receive the command sent by the bridge tothe storage device and route the command signal to the storage device.In this case, the multiplexing device may be directly coupled to thestorage device and the bridge chips (e.g. using a bus, etc.). Themultiplexing device may also be indirectly coupled to the storage deviceand the bridge chips (e.g. through an intermediate device, etc.).

In another embodiment, a command or data may be received by one of thebridges in a first format associated with a first protocol (e.g. a SATAprotocol, etc.). In this case, the storage device may have sent thecommand or data. The bridge may then translate the command or data to asecond format associated with a second protocol (e.g. an SAS protocol,etc.).

The bridge may then send the command to another device coupled to, or incommunication with, the bridge. A multiplexing device may then receivethe command or data sent by the storage device to the bridge and routethe command signal to the appropriate bridge.

FIG. 7 illustrates an exemplary system 700 in which the variousarchitecture and/or functionality of the various previous embodimentsmay be implemented. As shown, a system 700 is provided including atleast one host processor 701 which is connected to a communication bus702. The system 700 also includes a main memory 704. Control logic(software) and data are stored in the main memory 704 which may take theform of random access memory (RAM).

The system 700 also includes a graphics processor 706 and a display 708,i.e. a computer monitor. In one embodiment, the graphics processor 706may include a plurality of shader modules, a rasterization module, etc.Each of the foregoing modules may even be situated on a singlesemiconductor platform to form a graphics processing unit (GPU).

In the present description, a single semiconductor platform may refer toa sole unitary semiconductor-based integrated circuit or chip. It shouldbe noted that the term single semiconductor platform may also refer tomulti-chip modules with increased connectivity which simulate on-chipoperation, and make substantial improvements over utilizing aconventional central processing unit (CPU) and bus implementation. Ofcourse, the various modules may also be situated separately or invarious combinations of semiconductor platforms per the desires of theuser.

The system 700 may also include a secondary storage 710. The secondarystorage 710 includes, for example, a hard disk drive and/or a removablestorage drive, representing a floppy disk drive, a magnetic tape drive,a compact disk drive, etc. The removable storage drive reads from and/orwrites to a removable storage unit in a well known manner.

Computer programs, or computer control logic algorithms, may be storedin the main memory 704 and/or the secondary storage 710. Such computerprograms, when executed, enable the system 700 to perform variousfunctions. Memory 704, storage 710 and/or any other storage are possibleexamples of computer-readable media.

In one embodiment, the architecture and/or functionality of the variousprevious figures may be implemented in the context of the host processor701, graphics processor 706, an integrated circuit (not shown) that iscapable of at least a portion of the capabilities of both the hostprocessor 701 and the graphics processor 706, a chipset (i.e. a group ofintegrated circuits designed to work and sold as a unit for performingrelated functions, etc.), and/or any other integrated circuit for thatmatter.

Still yet, the architecture and/or functionality of the various previousfigures may be implemented in the context of a general computer system,a circuit board system, a game console system dedicated forentertainment purposes, an application-specific system, and/or any otherdesired system. For example, the system 700 may take the form of adesktop computer, lap-top computer, and/or any other type of logic.Still yet, the system 700 may take the form of various other devicesincluding, but not limited to, a personal digital assistant (PDA)device, a mobile phone device, a television, etc.

Further, while not shown, the system 700 may be coupled to a network[e.g. a telecommunications network, local area network (LAN), wirelessnetwork, wide area network (WAN) such as the Internet, peer-to-peernetwork, cable network, etc.] for communication purposes.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example only, and notlimitation. Thus, the breadth and scope of a preferred embodiment shouldnot be limited by any of the above-described exemplary embodiments, butshould be defined only in accordance with the following claims and theirequivalents.

What is claimed is:
 1. An apparatus comprising: a memory; acommunication bus coupled to a device; and a processor communicativelycoupled to the communication bus and the memory, the processorconfigured to implement storage traffic between a storage device and acentral processor via a first storage port of a first bridge chip of aplurality of bridge chips, the first bridge chip comprising a pluralityof ports organized as a plurality of groups comprising a first portgroup, a second port group, and a third port group, multiplex, by thefirst bridge chip, the storage traffic to at least one bridge chip ofthe plurality of bridge chips, and distribute data across the pluralityof bridge chips to produce a data distribution enabling each of thebridge chips to communicate with each other.
 2. The apparatus of claim1, wherein the first bridge chip is configurable to assume a firstconfiguration such that information from the storage device presented tothe first port group is sent to a selected one of the second port groupand the third port group and is further configurable to assume a secondconfiguration such that information from the storage device presented tothe first port group is sent to the second port group and the third portgroup.
 3. The apparatus of claim 1, wherein the processor is furtherconfigured to, responsive to a condition in which all resources of oneof the plurality of bridge chips are in use, distribute data acrossother bridge chips of the plurality of bridge chips.
 4. The apparatus ofclaim 1, wherein the first port group is a mass-storage-side port group,and the second port group and the third port group aremass-storage-utilizing-side port groups.
 5. The apparatus of claim 1,wherein performance of the multiplexing of the storage traffic is basedupon a combination of protocol translation resources of the plurality ofbridge chips.
 6. The apparatus of claim 1, wherein the storage device iscompatible with a first storage protocol and the central processor iscompatible with a second storage protocol, and wherein the processor isfurther configured to provide interoperation between the storage deviceand the central processor.
 7. The apparatus of claim 1, wherein aperformance of a selected one of the multiplexing of first storagetraffic and the multiplexing of second storage traffic is based upon acombination of protocol translation resources of the plurality of bridgechips.
 8. The apparatus of claim 1, wherein each of the bridge chipscommunicates with each other via a plurality of communication links, andwherein at least one communication link of the plurality ofcommunication links is configured such that each of the plurality ofbridge chips is capable of communicating with each other of theplurality of bridge chips.
 9. The apparatus of claim 1, wherein at leastone communication link of the plurality of communication links isconfigured to be utilized for error recovery.
 10. The apparatus of claim1, wherein at least one communication link of the plurality ofcommunication links is configured to be utilized for vendor uniquecommunication.
 11. The apparatus of claim 1, wherein at least one of theplurality of groups of ports of the at least one of the plurality ofbridge chips configured to multiplex storage traffic comprises aplurality of input ports.
 12. A method, comprising; implementing storagetraffic between a storage device and a central processor via a firststorage port of a first bridge chip of a plurality of bridge chips, thefirst bridge chip comprising a plurality of ports organized as aplurality of groups comprising a first port group, a second port group,and a third port group; multiplexing, by the first bridge chip, thestorage traffic to at least one bridge chip of the plurality of bridgechips; and distributing data across the plurality of bridge chips toproduce a data distribution enabling each of the bridge chips tocommunicate with each other.
 13. The method of claim 12, wherein thefirst bridge chip is configurable to assume a first configuration suchthat information from the storage device presented to the first portgroup is sent to a selected one of the second port group and the thirdport group and is further configurable to assume a second configurationsuch that information from the storage device presented to the firstport group is sent to the second port group and the third port group.14. The method of claim 12, further comprising distributing data acrossother bridge chips of the plurality of bridge chips responsive to acondition in which all resources of a particular one of the plurality ofbridge chips are in use.
 15. The method of claim 12, wherein the firstport group is a mass-storage-side port group, and the second port groupand the third port group are mass-storage-utilizing-side port groups.16. The method of claim 12, wherein performance of the multiplexing ofthe storage traffic is based upon a combination of protocol translationresources of the plurality of bridge chips.
 17. A system comprising: astorage device; a multiplexing bridge chip configured to multiplex dataand to distribute data, the multiplexing bridge chip comprising aplurality of ports organized as a plurality of groups comprising a firstport group, a second port group, and a third port group, the first portgroup being a mass-storage-side port group, the second port group andthe third port group being mass-storage-utilizing-side port groups; afirst bridge chip and a second bridge chip connected to the multiplexingbridge chip, the first bridge chip and the second bridge chip eachconfigured to distribute data, a first output port associated with thefirst bridge chip; a second output port associated with the secondbridge chip; and a communication link connecting the storage device tothe multiplexing bridge chip and allowing information from the storagedevice presented to the first port group to be sent to a selected one ofthe second port group and the third port group.
 18. The system of claim17, wherein the communication link is a first communication link, andwherein the first bridge chip and the second bridge chip are connectedby a second communication link.
 19. The system of claim 18, wherein themultiplexing bridge chip is a first multiplexing bridge chip, the firstmultiplexing bridge chip is connected to a second multiplexing bridgechip by a third communication link, the second multiplexing bridge chipis configured to multiplex data and to perform protocol translations,and the first and second multiplexing bridge chip are connected to amultiplexer to perform additional multiplexing functionality.
 20. Thesystem of claim 17, wherein performance of the multiplexing of storagetraffic is based upon a combination of protocol translation resources ofthe plurality of bridge chips.